Universal computer architecture

ABSTRACT

A universal computer for a vehicle, comprising a microprocessor for the processing of control programs, a storage unit, for the data thus calculated and an interface which permits a connection of the computer to a databus in the vehicle. The computer comprises control programs for controlling device provided in the vehicle, whereby the control commands are transmitted to the device to be controlled via device interfaces. The computer also comprises reconfigurable hardware, which permits a retroactive reconfiguration of peripheral components or an interface in the assembled state of the computer. A transmission of an algorithm for reconfiguration of the hardware is provided to the storage unit on the vehicle, so that a process for reconfiguration of the hardware associated with the peripheral components or the interface may be carried out.

BACKGROUND AND SUMMARY OF THE INVENTION

This application claims the priority of German patent document 101 39610.4, filed 11 Aug. 2001 (PCT International Application No.PCT/EP02/06251), filed Jun. 7, 2002 the disclosure of which is expresslyincorporated by reference herein.

The invention relates to a universal computer for vehicle, having amicroprocessor for processing control programs, a storage means for thedata which is calculated in the process, and an interface which permitsthe computer to be connected to a vehicle data bus. The computer hascontrol programs for controlling vehicle devices and device interfacesthat transmit control instructions to the devices that are to becontrolled.

German patent document DE 197 48 536 C2 discloses a computer for avehicle, which is provided with a microprocessor, various storage meansand an interface which permits connection to a CAN bus. Such controldevices ordinarily also have interfaces via which various devices, suchas a mobile telephone or a navigation device, can be coupled.

A disadvantage of the conventional control devices is that the computersremain installed in the vehicle during its entire service life, so thatthe hardware of the computers is predefined. Subsequent exchange of thehardware in a vehicle which is in use cannot be carried out incontemporary network systems (with up to 60 computers in a vehicle), dueto the high degree of expenditure on configuration. As a result,hitherto all that has been considered is to exchange various softwaremodules during the service life of the vehicle so that the software isadapted to changing in conditions.

It is then necessary also to configure parts of the hardware in a waywhich can be flexibly adapted. In particular in the telecommunicationsmarket (for example in the case of mobile telephones), the design of thehousings and interfaces are changed frequently. Thus, it is virtuallyimpossible to subsequently connect a relatively modern mobile telephoneto a control device in the vehicle.

German patent document DE 197 50 662 A1 discloses a processor unit for adata processing protected electronic control system in a motor vehicle,in which the computer is a scaleable arithmetic unit (i.e., a piece ofhardware which is designed to meet the power requirements with differentprocessor power); and depending on the demands, it can be replaced witha faster or slower microprocessor. If a relatively high processor poweris called for, the microprocessor can then be replaced by a morepowerful one, it being possible to plug the scaleable processor into thesame processor connector. However, the hardware is replaced in itsentirety, which is possible if the control devices are opened, thehardware exchanged and the software programs correspondingly input.

Reconfigurable hardware in the form of field programmable gate arrays(FPGA) are disclosed, for example, in U.S. Pat. Nos. 5,457,410 and6,014,509, and in International Patent Document WO 95/28769. These FPGAshave memory cells such as flip flops which can also change theirfunction after manufacture. The memory cells are freely configurablewith one another, electrically conductive connections being newly wiredso that diverse logical circuits can be established. By means of suchFPGAs it is possible to simulate logic circuits and in particular toconstruct electrical filters, or they can be used simply as storagemeans.

An article in Elektronik [Electronics] July 1998, page 38, entitled “Mitprogrammierbarer Logik verheiratet [Wedded to programmable logic]”discloses that an FPGA field is provided as reprogrammable hardware inorder to perform complex computing tasks.

European Patent Document EP 801 351 A2 discloses a microprocessor withinterface modules which have FPGAs. The use of FPGAs makes it possibleto reconfigure these interface modules to adapt to different components.

One object of the present invention is to provide a universal computerfor a vehicle, which is suitable for use with a data bus and othercontrol devices, can be adjusted within the vehicle without changing thehardware, to new interface requirements or subsequently interchangeabledevices, and at the same time provides a specific storage region of thealgorithm for configuring the hardware.

This and other objects and advantages are achieved by the computeraccording to the invention, which has transmission means that transmitan algorithm for reconfiguring the hardware to the storage means in thevehicle so that the hardware which relates to the peripheral componentsor the interface can be reconfigured. A storage control means isprovided which automatically transmits the algorithm for reconfiguringthe hardware to the storage means in the vehicle, and a memory isprovided in which a plurality of data pages for configuring the hardwareare stored. Only one of these data pages is classified as valid as inthe present device configuration, and the storage control meansretrieves the applicable data pages in accordance with theconfiguration.

According to the present invention, the computer is installed in thevehicle in the form of a control device when the vehicle ismanufactured. Together with other control devices, it forms a networkwithin the vehicle. The various control devices can communicate with oneanother via the data bus, and control programs are provided foractuating, via device interfaces, devices which can be coupled to thenetwork.

According to the invention reconfigurable hardware is used, which can bereconfigured by downloading an algorithm, even years after the vehiclehas been delivered to the customer. The algorithm may be a hardwaredescription language which describes the configuration of the respectivehardware. Such reconfigurable hardware is used in particular in allinterfaces and peripheral components which are frequently affected byhardware changes. “Peripheral components” is understood to meaninterrupt controllers, logic modules and circuits as well as filters andoutput stage actuation circuits, which control devices which areconnected. In addition, these include interface drivers, addressingcomponents, devices for actuating data buses or logic units forcontrolling storage. The microcomputer itself can also be simulated byan FPGA module.

For example, a central vehicle display is arranged in the interior ofthe vehicle and can be actuated by means of a control device. Varioustelematics devices (for example a mobile telephone, a navigation systemor various audio or video devices) are connected to the vehicle networkvia a device interface. If an additional device is then connected to thenetwork or a control device or a relatively old device is replaced witha device according to a new standard, on the one hand the necessarydriver software is transmitted from the outside to a storage means inthe computer using a transmission means. However, on the other hand, thewiring between the device interface and the computer can also be changedby the reconfigurable hardware using an algorithm for reconfiguring thehardware so that it is unnecessary to exchange the entire deviceinterface, as is customary, but rather the hardware can be reconfigured.Furthermore, various digital filters and logic circuits can bereconfigured or newly connected by virtue of the fact that an algorithmfor reconfiguring a service center is transmitted to the storage meansof the computer.

In this way, a plurality of configuration algorithms for the FPGA can bestored in a storage area of the computer, and the FPGA module isconfigured by the storage control means by means of a memory access. Thestorage control means can then access the currently applicable data pageat the same memory address, and configures the FPGA hardwarecorrespondingly. In a memory addressing area in the memory, thecurrently applicable data page is respectively superimposed on the otherpages which could be used as an alternative for configuring thehardware, but are not currently required owing to the existing devicecircuitry.

The advantage of this new universal computer architecture is thatspecific hardware elements can be reconfigured so that standard logicelements and their wiring can be changed or subsequently rewired. Inthis way, in future, hardware will no longer need to be exchanged if newdevices are retrofitted in the vehicle; rather the hardware can becorrespondingly adapted by means of an algorithm for reconfiguring thehardware. In this way, it is not necessary to provide new hardwarewhenever a device is changed, because it can be adapted by means of thereconfigurable hardware when new devices are used. On the other hand, itis also possible to adapt the long-life computer architecture which ispresent in the vehicle to new conditions by reconfiguring itsfunctionality.

The reconfigurable hardware preferably has freely connectable memorycells with reconfigurable electrical connections which can besubsequently newly connected in accordance with the algorithm forreconfiguring the hardware in the installed state of the vehicle. Thereconfigurable hardware may be a FPGA that is either ROM-based (in whichcase information is retained when the power fails and the hardware canbe changed by means of ultraviolet light or electronic processes) orRAM-based (whose information is lost when the power fails). Such FPGAscan be appropriately reprogrammed by means of an algorithm, for examplea set of instructions for programming digital logic functions. FPGAs canalso be used as state machines. Here, the signals assume various,permanently predefined states such as are also implemented today inmeans of transportation in the form of state machines.

In one preferred embodiment of the invention, the microprocessor of thecomputer has standard cell blocks (SCB), and is constructed from variouspredefined logic blocks, so that logic components from variouselectronic manufacturers can be combined in one microprocessor andimplemented in the form of what is referred to as a user specific module(ASIC). The invention then combines advantages of a standard cell blockmicroprocessor core with reprogrammable hardware, and it is possible totransmit the software and algorithms for reconfiguring the hardware to astorage means of the computer over a wire-free interface. Using theinformation which is transmitted from a service center over thewire-free interface, it is then possible to reconfigure the universalcomputer in terms of hardware in accordance with the algorithms and thusadapt it to new external devices or further hardware requirements.

In another embodiment of the invention, a storage control means isprovided which, without affecting the processor time of themicroprocessor, transmits the algorithm for reconfiguring the hardwareto the storage means in the means of transportation automatically. Ifnecessary, when triggered by a service center or the microprocessor, thestorage control means can request transmission of the algorithms for thereconfiguration of the hardware and then store the result data in whatis referred to as a flash memory, for example. The wire-free interfacevia which the data can be transmitted to the computer may beimplemented, for example, in a GSM Standard or according to theBluetooth Standard. The storage control means according to the presentinvention thus relieves the loading on the computer which is occupiedwith control programs when it is operating, and transmits the algorithmsfor reconfiguring the hardware into a flash memory independently of themicroprocessor. A flash memory is suitable for long-term storage of datawhich can be transmitted from a service center to the means oftransportation. By transmitting the reconfiguration algorithms over awireless interface and reading in the data as well as algorithms intothe flash memory, a highly flexible and effective computer architectureis produced which permits later reconfiguration of the hardware.

As the microcomputer is preferably composed of standard cell blocks, thehardware structures can be modularized and also easily transferred toreconfigurable hardware (FPGA). Such standard cell blocks are theneliminated from the microcomputer hardware and programmed in the form ofFPGAs by means of the reconfiguring algorithms. The standard cell blockscan, however, also be provided within the microprocessor which can thenbe wired in a variable fashion to a device interface via thereconfigurable hardware. On the other hand, the reconfigurable hardwarecan also be arranged as a peripheral device next to the microprocessorand can carry out the wiring and the processing of the electricalsignals.

The storage control means can be responsible not only for the control ofdata transmission but also for data protection. All the data which istransmitted to the computer via the interfaces (for example the deviceinterfaces or the interface for transmitting the algorithm forreconfiguration) can, for this purpose, run via the storage controlmeans. The storage control means then checks a specific enabling numberor private and public keys according to an encryption method, and thedata (i.e., the algorithm for reconfiguring the hardware) cannot betransmitted to the computer until there is a positive check. If analgorithm is to be transmitted from an external service center or from adevice which is coupled to the device interface to the computer, first arequest for the transmission of the reconfiguration data may benecessary.

In addition, after the microprocessor has been powered up, an enablesignal to the storage control means may be necessary in order to signalthat the system is ready for an external data transmission, and thestorage control means can independently carry out the transmission of analgorithm to the flash memory or to an overlay memory. It is possible toprovide a state in which an external transmission of hardware algorithmsis completely prohibited.

If, for example, hardware configuration data are stored in a specificmemory area of a memory, it is possible to provide that all such datacan be retrieved at the same address, with only one of the memory pages(representing the present hardware configuration for a device which isconnected) being active. The other data pages may provide algorithms inthe form of a hardware configuration language if another device is to beconnected. Then, only one of the previously inactive memory pages isactivated, as a result of which the hardware configuration for the newdevice is automatically set. The reconfigurable module is automaticallyrewired by the hardware description language with respect to theconnections between the individual memory cells, and wired differentlywith respect to the memory cells. As a result, for example, theinterface is configured with a new pin to pin connection.

Other objects, advantages and novel features of the present inventionwill become apparent from the following detailed description of theinvention when considered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The single FIGURE is a diagram showing a schematic view of variousfunctional blocks according to an embodiment of the universal computeraccording to the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

The universal computer according to the present invention has amicroprocessor 1, an FPGA module 2 as reconfigurable hardware and astorage device 3 in which the data calculated or read in can be storedvia the data storage path 4. In addition, a floating point unit 5, forcalculating sliding decimals, and a bus interface unit 6, which cantransmit the data within the computer via the internal bus or cancontrol the transmission of data, are provided. In order to control theperipheral devices and evaluate specific signals, an interruptcontroller 8 provided on the internal data bus 7 controls programs withthe support of a watchdog unit 9 and a timer.

The internal data bus 7 is connected via what is referred to as a bridge10 to the internal data bus 11 in order to actuate the peripheralcomponents and various interfaces 15–19, including a real-time controldevice 12, a further timer 13 for variable use, a pulse-width modulator14 and a plurality of device interfaces 15, 16 as well as a plurality ofdata bus interfaces 17–19. One of the data bus interfaces 17 is a CANbus interface, a further interface 19 being suitable for connecting anoptical data bus. A wireless interface 20 is provided, in particularaccording to the Bluetooth Standard, in order to store software, dataand algorithms for reconfiguring the hardware in a wireless fashion on aflash memory 21. In particular a hardware description language, forexample according to the Verilog Standard, is used as the algorithm forreconfiguring the hardware.

A storage control means 22 is provided for automatically transmittingthe reconfiguration algorithm, the data or software to the flash memory21 in the means of transportation. The storage control means 22 cancarry out the transmission of data via the Bluetooth interface 20independently of the microprocessor 1, so that the microprocessor 1 canuse its computing time for the control processes from outside to thedevices connected to the interfaces 15–19. The flash memory 21 isprovided for loading a special software item that permits, on the onehand, the reprogramming algorithm of the FPGA and on the other hand theinitialization of the FPGA module 2 at the beginning during normaloperation. In addition, the storage control means 22 can transmitdata-synchronously or asynchronously with respect to a computing processinto the microprocessor 2 from the storage means 3.

The storage control means 22 provides a flash memory reprogramming modein which an authorization check for the transmission of data is firstcarried out, and, when authorization is given it provides foralgorithms, data or software to be transmitted into the flash memory 21.The storage control means 22 also provides an FPGA reconfiguration mode,in which a first authorization check of the system user is also carriedout and a reconfiguration algorithm is then loaded. An algorithm may bewritten, for example, in the hardware description language (HDL) therebeing a description there of the way in which the hardware isreconfigured.

The storage control means 22 can also actuate specific memories whichstores algorithms and data on data pages, which are assigned a selectionvalue. At each access time, only that page which is valid at thatparticular time after the selection value, is taken into account by thestorage control means 22. In this way, a plurality of configurationalgorithms for the FPGA 2 can be stored in a memory area, and the FPGAmodule 2 is configured by a memory access by the storage control means22. Depending on the selection value, the storage control means 22 thenaccesses the data page which is valid at that particular time at thesame memory address and configures the FPGA hardware 2 accordingly. In amemory address area in the memory, the data page which is valid at thatparticular time is superimposed on the other pages which could be usedas an alternative for configuring the hardware, but are not required atthat particular time owing to the device wiring which is present.

One possible way of reconfiguring the hardware 2 is to change theinterfaces 17–19 to the data bus. In this case, the wiring of theindividual logic elements of the interface modules 17–19 is changed andis then embodied in the form of FPGA memory cells 2. For example, theinterface 19 can be adapted to a new data bus by reconfiguring thehardware. On the other hand, however, an interface 16 can also beadapted to a new device so that the logic cells and the wiring in theinterface module 16 are changed. The greater the number of devices inthe network, the more reconfiguration processes may be necessary duringthe lifetime of a vehicle. For this purpose it is possible to have thatthe devices themselves already provide a suitable algorithm forreconfiguring the hardware, which is then transmitted to the storagecontrol means 22 via the corresponding interface and automaticallyprovides reconfiguration of the interface modules 15 to 19. Thisautomatic reconfiguration of the hardware 2 may be carried out by thestorage control module 22 after an authorization check.

The universal computer according to the invention, can be designed toreconfigure its own architecture and to reconfigure the networkactuation means. For example, on the basis of the computer architecture,it is possible to change the wiring to the interfaces 15–19 or thewiring between the individual devices. On the other hand, the interfacescan be automatically adapted to devices if they make available analgorithm for reconfiguring and transmitting the computer architecture,and the storage control means 22 automatically provides, on the basis ofthese algorithms, for the circuits which are embodied in FPGA 2 to bereconfigured.

The foregoing disclosure has been set forth merely to illustrate theinvention and is not intended to be limiting. Since modifications of thedisclosed embodiments incorporating the spirit and substance of theinvention may occur to persons skilled in the art, the invention shouldbe construed to include everything within the scope of the appendedclaims and equivalents thereof.

1. A universal computer for a vehicle, said universal computercomprising: a microprocessor for processing control programs; a storageunit for data calculated during processing of the control programs; aninterface for connecting the computer to a vehicle data bus; controlprograms for controlling devices provided in the vehicle, whereincontrol instructions are transmitted via device interfaces to thedevices to be controlled; reconfigurable hardware which permitssubsequent reconfiguration of peripheral components or of an interfacein an installed state of the computer; transmission means which transmitan algorithm, for reconfiguring the hardware, to the storage unitwhereby a process for reconfiguring the hardware with regard to theperipheral components or to the interface can be carried out; a storagecontrol unit which automatically transmits the algorithm forreconfiguring the hardware to the storage unit; and a memory in which aplurality of data pages for configuring the hardware are stored, whereinonly one of the data pages is classified as valid in a present deviceconfiguration and wherein the storage control unit retrieves applicabledata pages during a reconfiguration.
 2. The computer as claimed in claim1, wherein the reconfigurable hardware has freely connectable memorycells with reconfigurable electrical connections which can besubsequently newly connected in accordance with the algorithm forreconfiguring the hardware in the installed state of the computer. 3.The computer as claimed in claim 1, wherein the reconfigurable hardwarecomprises a field programmable gate array.
 4. The computer as claimed inclaim 1, wherein the storage control unit transmits the algorithm forreconfiguring the hardware to the storage unit without affecting aprocessor time of the microprocessor.
 5. The computer as claimed inclaim 1, wherein the storage unit comprises a flash memory which isconnected to a wireless interface via which the algorithm forreconfiguring the hardware can be transmitted into the flash memory. 6.The computer as claimed in claim 1, wherein part of the computer iscomposed of standard cell blocks which are embodied as reconfigurablehardware.
 7. The computer as claimed in claim 6, wherein themicroprocessor has standard cell blocks which can be wired via thereconfigurable hardware to an interface in a variable fashion.
 8. Thecomputer as claimed in claim 1, wherein data pages for the configurationof the hardware that is necessary for a device that is to be coupledexternally to the device interfaces is stored in the form of a hardwaredescription language for transmission to the computer in the device. 9.The computer as claimed in claim 8, wherein the device interfacetransmits the hardware description language for peripherals andinterfaces of the computer to at least one of the computer and thestorage control unit.
 10. The computer as claimed in claim 1, wherein: astorage control means is provided; and a transmission safety meanspermits a transmission of an algorithm for reconfiguring the hardware,only after a check to determine whether a utilized method of datatransmission is permissible in a present state of the vehicle or of thecomputer, and/or whether a sender is authorized to transmit a newalgorithm for reconfiguring the hardware.